US Patent 7257765 Rate dematching processor

(3n+1)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a first memory 102, (3n+2)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a second memory 103, and (3n+3)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a third memory 104. Information bit, first parity bit, and second parity bit that have been read out by 3 bits are held in an information bit queue 108, a first parity bit queue 109, and a second parity bit queue 110, respectively, to control data supply to the rate dematching circuits 111 and 112 by these queues 108, 109 and 110.