US Patent 7263009 Semiconductor memory device with delay section

In a semiconductor memory device, a reference delay section has a first delay value and delays a first signal by a reference delay value obtained from the first delay value and an adjustment value while changing the adjustment value, and fixes the adjustment value when the first signal and the delayed first signal meet a predetermined condition. A delay section has a second delay value and generates an output signal based on a summation of the fixed adjustment value and the second delay value, and a set multiplication value in response to a trigger signal such that the output signal in an active state for a period corresponding to the set multiplication value.