US Patent 7263572 Bus bridge and data transfer method

In response to a direct memory access (DMA) request, a direct memory access controller (DMAC) performs reading at a host side at which a high-speed bus master is arranged. A bus bridge sends a dummy data to the DMAC, and performs reading at an input/output (I/O) side at which a low-speed slave device is arranged. In response to a following DMA request, the DMAC performs reading at the host side. The bus bridge sends a data read for a previous DMA request at the I/O side to the DMAC, and performs reading at the I/O side. Data that is read in response to a final DMA request at the I/O side is stored in a buffer inside the bus bridge. A central processing unit (CPU) reads a last read data from the buffer.