US Patent 7265041 Gate layouts for transistors

A transistor and a method of fabricating the transistor are provided. The transistor includes a semiconductor material comprising drain regions and source regions formed in alternating rows or columns. The transistor also includes polysilicon chains overlaying the top of the semiconductor material, disconnected from and substantially parallel to one another, and separating the drain regions from the source regions. The method includes providing a semiconductor material, growing a first insulating layer on top of the semiconductor material, depositing a polysilicon layer on top of the first insulating layer, defining a plurality of chains in the polysilicon layer, the plurality of chains being disconnected from and substantially parallel to one another, and forming a plurality of drain regions and a plurality of source regions in the semiconductor material in alternating rows or columns. The plurality of chains separates the plurality of drain regions from the plurality of source regions.