Patent attributes
A semiconductor memory device is composed of a plurality of banks each including a plurality of sub-arrays arranged in rows and columns; global I/O lines shared by the plurality of banks; local I/O lines disposed for every a number of sub-arrays within each of the plurality of banks; I/O switch control circuits responsive to respective I/O switch timing signals for establishing connections between the global I/O lines and the local I/O lines within each of the plurality of banks; and a timing control circuit. The timing control circuit controls the I/O switch timing signals that each I/O switch timing signal remains activated until associated one of the plurality of banks gets out of a row active state after once the each I/O switch timing signal is activated.
