US Patent 7274610 Semiconductor memory device

Disclosed is a semiconductor memory device equipped with an on-chip comparison and latching function, including a latch circuit which receives a comparison result signal, output from a compare circuit receiving read data signals from plural data bus signals and an input data signal from outside and comparing whether or not the signals coincide with each other, to output the result of latching of the fail information based on a control signal. The latch circuit latches and outputs the fail information of a preset number bit output from the compare circuit during the time when a control signal for latching and outputting the fail information is in active state.