US Patent 7277342 Semiconductor memory having dummy bit line precharge/discharge circuit

Reset dummy cells which change the load capacitance of a dummy read line DRD according to stored information are provided. Memory information are set to the reset dummy cells according to environmental factors, such as the temperature condition, voltage condition, etc. The timing of reading data from memory cells is controlled according to a change in voltage of the dummy read line DRD which is caused due to the discharge of the precharged dummy read line DRD.