US Patent 7277909 High speed adder

Provided is an adder composed of (N+1) circuit stages in the ease of 2.sup.N bits. In the case of N=4 (that is, 16 bits), provisional carries that indicate the case where carry is produced from a low order bit and the case where no carry is produced therefrom are generated by conditional cells in a first circuit stage. In second to fourth circuit stages, the provisional carries corresponding to higher seven bits other than the most significant bit are converted into provisional sums by converters in a circuit stage in which the provisional carries are transferred. In addition, actual carry signals are selected from the provisional carries corresponding to lower seven bits other than the least significant bit in a circuit stage in which the provisional carries are transferred. In a fifth circuit stage, bit sums for each of the bits are generated and outputted.