US Patent 7279745 Semiconductor device

In a semiconductor device of the present invention, an N-type epitaxial layer 2 is deposited on a P-type substrate 1. In the epitaxial layer 2, a P-type diffusion layer 5 to be used as a back gate region is formed. An N-type diffusion layer 8 to be used as a drain region is formed so as to surround the P-type diffusion layer 5. The P-type diffusion layer 5 and the N-type diffusion layer 8 partially overlap with each other. By use of a structure described above, a distance between a drain and a source is shortened. Thus, an ON resistance value can be reduced. Moreover, since a concentration gradient can be generated in the drain region, withstand pressure characteristics can be maintained while reducing an element formation region.