Patent attributes
An electron emission device includes gate electrodes formed on a substrate. The gate electrodes are located on a first plane. An insulating layer is formed on the gate electrodes. Cathode electrodes are formed on the insulating layer. Electron emission regions are electrically connected to the cathode electrodes. The electron emission regions are located on a second plane. In addition, the electron emission device includes counter electrodes placed substantially on the second plane of the electron emission regions. The gate electrodes and the counter electrodes are for receiving a same voltage, and a distance, D, between at least one of the electron emission regions and at least one of the counter electrodes satisfies the following condition: 1(μm)≦D≦28.1553+1.7060t(μm), where t indicates a thickness of the insulating layer.
