Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Chao-Hsin Lu0
Date of Patent
October 9, 2007
Patent Application Number
11268505
Date Filed
November 8, 2005
Patent Primary Examiner
Patent abstract
A clock signal generator and method thereof are provided for a system to generate an output signal. The apparatus comprises: a delay circuit for generating a delayed clock with a first time, a delay module for generating delayed signal(s), and a decision circuit for comparing the delayed signal(s) with the delayed clock to obtain the relative relation between the delay time and the first time and controlling a delay time of an input signal according to the relative relation to generate the output signal.
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