Patent attributes
A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of pads disposed on the active surface and electrically connected to the optical component; the pad extension traces are electrically connected to the pads; the via holes are formed through the chip and electrically connected to the pad extension traces; the lid is attached on the active surface of the chip; and the plurality of metal traces are disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defines a plurality of solder pads thereon.
