US Patent 7285451 Semiconductor integrated circuit device manufacturing method

To reduce variation in channel lengths of MOS transistors within a circuit functional module. When exposure of a wafer substrate having a semiconductor integrated circuit device 1 including a plurality of CMOS circuit module regions CCM11 to CCM22 to be subject to substrate bias control formed in a core region 10 is performed using a step-and-scan type projection exposure apparatus, scanning is performed in the same direction as a longitudinal direction of the respective CMOS circuit module regions CCM11 to CCM22. In this device, a gate insulating film is formed on the substrate, a gate electrode material film is formed on the gate insulating film, and a photoresist film is formed on the gate electrode material film.