US Patent 7285986 High speed, low power CMOS logic gate

A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an inverter. The gate uses high speed, low threshold voltage devices in the evaluation stage, yet uses higher threshold voltage devices in other portions of the gate (e.g., precharge circuitry). This use of dual threshold voltage devices minimizes power consumption while maximizing speed. During standby mode, the gate is operated in an evaluation mode to substantially mitigate standby current.