US Patent 7286423 Bit line precharge in embedded memory

An integrated circuit device includes a first latch having a first input to receive a first predecode value, a second input to receive a first clock signal, and an output to provide a latched first predecode value responsive to an edge event of the first clock signal. The integrated circuit device further includes a memory component. The memory component includes an input to receive the latched first predecode value and the latched second predecode value, a first bit line, and a plurality of word lines coupled to the first bit line. Each word line is associated with a corresponding bit of the latched second predecode value. The integrated circuit device further includes logic having an input to receive the corresponding bit of the latched first predecode value. The logic is to precharge the first bit line directly responsive to only a value at the corresponding bit of the latched first predecode value.