Patent attributes
A plasma display panel, which enables low voltage addressing and reduces deterioration of the fluorescent layers, thereby achieving excellent luminance, includes: a front substrate having sustaining electrodes arranged at predetermined intervals; a front dielectric layer adapted to bury the sustaining electrodes; a rear substrate facing the front substrate and including address electrodes arranged orthogonal to the sustaining electrodes; a rear dielectric layer adapted to bury the address electrodes; barrier walls adapted to define stripe-shaped discharge spaces arranged between the front substrate and rear substrate, the stripe-shaped discharge spaces being parallel to and alternating with the address electrodes; fluorescent layers arranged within the discharge spaces; and at least one floating electrode respectively arranged within the barrier walls in a longitudinal direction of the barrier walls. Alternatively, first and second barrier walls can be adapted to define discharge spaces arranged between the front substrate and rear substrate, the first barrier walls arranged parallel to and alternating with the address electrodes, and the second barrier walls arranged perpendicular to the first barrier walls and at least one floating electrode respectively arranged within the first and second barrier walls and in a longitudinal direction of the first and second barrier walls.
