Patent attributes
There is provided an analog-to-digital conversion apparatus that corrects digital data output from a plurality of analog-to-digital conversion units. The analog-to-digital conversion apparatus includes an interleaving unit operable to align the digital data respectively output from the plurality of analog-to-digital conversion units and to generate a data sequence; and a correction arithmetic unit operable to correct a data value error caused by a phase error of the sampling timing of the plurality of analog-to-digital conversion units based on a frequency characteristic of each of the analog-to-digital conversion units, in which the correction arithmetic unit includes: a data partitioning unit that generates a plurality of partition data by partitioning the data sequence; a data inserting unit that inserts data with data value zero at the head or end of each of the partition data by a predetermined insertion data number to sequentially output these data; an arithmetic unit that sequentially outputs data after correction made by sequentially performing correction arithmetic with respect to the partition data sequentially output from the data inserting unit; and a data connecting unit that adds the data of the insertion data number at the end of each data after correction and the data of the insertion data number at the head of the data after correction following that data after correction in order to sequentially connect that data after correction and the data after correction following that data after correction.
