US Patent 7294884 Passivation of power semiconductor device

A vertical power semiconductor device comprises a substrate including a first layer that is a first conductivity type. A first conductive region is provided proximate an upper surface of the substrate, the first conductive region being a second conductivity type that is different from the first conductivity type. A first electrode is provided proximate the upper surface of the substrate and coupled to the first conductive region. A second electrode is provided proximate a lower surface of the substrate. A passivation structure including first and second dielectric layers provided over the upper surface of the substrate. One or more field plates of first type are provided between the first and second dielectric layers.