Patent attributes
A circuit for timing adjustment includes a PLL circuit configured to generate a phase-adjusted clock signal in response to phase comparison between an input clock signal and a delayed clock signal, a feedback path configured to delay the phase-adjusted clock signal for provision as the delayed clock signal to the PLL circuit, a first timing correction circuit configured to add a predetermined delay time to the feedback path, an output data circuit configured to supply output data at first timing responsive to the phase-adjusted clock signal, a second timing correction circuit configured to delay the first timing by the predetermined delay time to generate second timing different from the first timing, and an input data circuit configured to latch input data at the second timing.
