US Patent 7298223 Methods and systems for electronic component test time improvement

A timer circuit that has a normal mode and a test mode is disclosed. The test mode includes a power-up phase and a power-down phase. The timer circuit includes an oscillator and a first timer circuit portion coupled to the oscillator. The first timer circuit portion includes an input and an output. An output signal that confirms either the satisfactory or unsatisfactory operation of the first timer circuit portion is taken from the output associated with the first timer circuit portion in the power-up phase. The timer circuit further includes a second timer circuit portion coupled to the first timer circuit portion and the oscillator. The second timer circuit portion also includes an input and an output. An output signal that confirms either the satisfactory or unsatisfactory operation of the second timer circuit portion is taken from the output associated with the second timer circuit portion in the power-down phase.