US Patent 7299318 Method for reducing cache conflict misses

An invention is provided for reducing cache conflict misses via specific placement of non-split functions and data objects in main memory based on cache size. A cache size of a computer cache memory is determined, and a first data block is placed within a main computer memory. The first data block includes a first sub-block that will be frequently referenced. In addition, the first sub-block ends at a first ending address. A second data block is then placed within the main computer memory. The second data block includes a second sub-block that will be frequently referenced, and is placed such that the second sub-block will be contiguous with the first sub-block in the computer cache memory during execution.