US Patent 7299438 Method and apparatus for verifying semiconductor integrated circuits

A timing verification apparatus calculates a pulse width variation coefficient based on a pulse width of an input clock signal, a delay value of the clock signal, and an operation frequency. The apparatus then calculates the pulse width for a delayed clock signal provided to a clock input terminal of a flip flop (FF) using the pulse width variation coefficient. Further, the apparatus compares the calculated pulse width with a standard value. The timing verification apparatus calculates the pulse width of the delayed clock signal provided to the clock input terminal of the FF using the pulse width of the clock signal, and a rise delay and a fall delay of the path. The apparatus considers on-chip variations and accurately executes timing verification for signals.