US Patent 7305712 Security mode switching via an exception vector

There is a provided a data processing system comprising:a processor operable in a plurality of modes and either a secure domain or a non-secure domain including:at least one secure mode being a mode in said secure domain; andat least one non-secure mode being a mode in said non-secure domain;whereinwhen said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and whereinsaid processor is responsive to a switching request to initiate a switch between a secure mode and a non-secure mode under control of a mode switching program starting at a location specified by an exception vector associated with said switching request.