US Patent 7308607 Periodic checkpointing in a redundantly multi-threaded architecture
Patent 7308607 was granted and assigned to Intel on December, 2007 by the United States Patent and Trademark Office.
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Patent abstract
A multithreaded architecture having one or more checker circuits that operate on store operations that send data outside of a sphere of replication. Fault detection mechanisms used to check outputs from the sphere of replication are reused for checkpointing at the conclusion of an execution epoch.
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US Patent 07308607 Periodic checkpointing in a redundantly multi-threaded architecture US Patent 7308607 Periodic checkpointing in a redundantly multi-threaded architecture
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Patent Number
0730860700
Patent Number
730860700
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Current Assignee
Patent Jurisdiction
Patent Number
073086070
Date of Patent
December 11, 2007
0Patent Application Number
106513880
Date Filed
August 29, 2003
0Official Website
Patent Primary Examiner
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Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
073086070
Date of Patent
December 11, 2007
0Patent Application Number
106513880
Date Filed
August 29, 2003
0Official Website
Patent Primary Examiner
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US Patent 07308607 Periodic checkpointing in a redundantly multi-threaded architecture
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07308607
Date of patent
December 11, 2007
Patent application number
10651388
Date Filed
August 29, 2003
Patent primary examiner
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