US Patent 7308666 Method and an apparatus to improve hierarchical design implementation

A method and an apparatus to improve hierarchical design implementation have been disclosed. In one embodiment, the method includes deriving boundary logic of at least one of a plurality of partitions in an integrated circuit (IC) design, marking the boundary logic of the at least one of the plurality of partitions based on at least one predetermined criterion, and performing implementation of the IC design using the marked boundary logic.