US Patent 7310006 Semiconductor integrated circuit

To provide an output MOS transistor from breaking due to dump surge and counter electromotive, a semiconductor integrated circuit according to an embodiment of the invention includes an output MOS transistor controlling current flowing through a load, a dynamic clamp circuit clamping an overvoltage applied to the output MOS transistor, a delay circuit generating a reference signal by adjusting a level of a gate voltage of the output MOS transistor, and a clamp controlling circuit making the dynamic clamp circuit operate based on the reference signal when a counter electromotive force is applied to the output MOS transistor.