Patent attributes
The present invention discloses a semiconductor memory having an array of storage cells with at least one PMOS transistor, the semiconductor memory comprising at least one mode bit for representing data stored in the array of storage cells are either true or inverted, a plurality of read-toggle drivers coupled on a plurality of data output paths for inverting the data outputs only when the mode bit indicates that the array of storage cells are storing inverted data, and a plurality of write-toggle drivers coupled on a plurality of data input paths for inverting the data inputs only when the mode bit indicates that the array of storage cells are storing inverted data and for writing back inverted data into the array of storage cells during a refreshing cycle.
