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Patent attributes
Current Assignee
0
Patent Jurisdiction
Patent Number
Patent Inventor Names
Andrew Paul Wallace0
Date of Patent
December 25, 2007
0Patent Application Number
107930360
Date Filed
March 5, 2004
0Patent Primary Examiner
Patent abstract
An adder-subtracter circuit being adapted to process two binary input numbers in order to generate the sum or the difference of the two processed numbers depending on the state of a subtract input signal. The circuit has the capability to feed back the result of the processing to itself in order to process one input number together with the result of a previous processing instead of the second binary number.
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