Patent attributes
A dual mode decoder which includes an MB810 decoder; an 8B/10B decoder; a mode detection unit, a first low pass filter; a second low pass filter; an IDLE code detection unit which detects IDLE code and transfers to the mode detection unit; a first switch unit which selectively outputs the 10-bit code input from the first low pass filter and the second low pass filter; a parallel conversion unit which outputs a 10-bit parallel code; a first selection unit which provides the 10-bit parallel code to the decoder determined as the operation decoder between the MB810 decoder and the 8B/10B decoder; and a second selection unit which selectively outputs an 8-bit code corresponding to the 10-bit parallel code input form the decoder determined as the operation decoder.
