US Patent 7315905 Software controlled hard reset of mastering IPS

A system-on-chip integrated circuit includes a peripheral initialization register has a bit corresponding to each module. Each bit indicates a normal mode or a reset mode for the corresponding module. A direct memory access unit can receive, prioritize and queue date movement transactions between modules and can read from or write to the peripheral initialization register. A peripheral interface unit prevents a write to the peripheral initialization register changing a module from reset mode to normal mode while there is an uncompleted data movement transaction involving that module. A false acknowledge circuit for each module supplies an acknowledge signal in response to a received command if the module is in reset mode.