US Patent 7317223 Memory device and method of manufacturing the same

In one embodiment, a memory device includes a semiconductor substrate, a first region formed in a predetermined region of the semiconductor substrate, and in which a plurality of memory transistors are disposed, and a second region adjacent to the first region, and in which a selection transistor is formed to supply a predetermined voltage to the memory transistor. The second region of the substrate may have a higher impurity concentration than an entire region of the substrate other than the second region. Reduced area of the selection transistor can be realized with a shortened channel length, without a decreased threshold voltage.