Is a
Patent attributes
Patent Jurisdiction
Patent Number
Date of Patent
January 22, 2008
Patent Application Number
11352179
Date Filed
February 10, 2006
Patent Primary Examiner
Patent abstract
A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.
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