US Patent 7323369 Fabrication method for thin film transistor array substrate

Scan lines are formed on a substrate. A patterned dielectric layer and a patterned semiconductor layer are formed to cover portions of the scan lines. A patterned transparent conductive layer and a patterned metal layer are sequentially formed to define data lines, source/drain electrodes, pixel electrodes and etching protecting layers. The etching protective layers cover the exposed scan lines exposed by the patterned dielectric layer and the patterned semiconductor layer, and are electrically connected to the scan lines. A passivation layer is formed, and then the passivation layer over the pixel electrodes and the patterned metal layer of the pixel electrodes are removed to expose the patterned transparent conductive layer. The patterned semiconductor layer over the scan lines between the etching protective layers and the data lines is removed to expose the patterned dielectric layer over the scan lines.