Patent attributes
The method and apparatus for analysis of integrated circuits using static timing analysis. For a circuit being analyzed, the value of the state net for the case of an undriven sensitization is resolved to a Hi/Lo logic on the output net and the sensitization is added to the appropriate pull-up/pull-down function on the output net. Furthermore, in the sensitization generation, the “present” state logic function at the output net is determined by the “previous” state variable of the sequential state net and the “present” state variables of the rest of the inputs to the sequential circuit. The “next” state logic function at the output net is determined by the “present” state variable of the sequential state net and the “next” state variables of the rest of the inputs to the sequential circuit. This variable is resolved as a function of “previous” state net variable and “present” state input net variables. In the present invention, a BDD XOR operation of the “present” state function and the “next” state function at the output net is used to determine the set of possible transitions at the output in terms of the transitions at the inputs. This function is further constrained with single input switching constraint. The resultant BDD describes the output net transition in terms of single input switching for every input to the sequential circuit.
