Patent attributes
A non-volatile memory device includes an array of flash memory cells therein and a voltage generator. The voltage generator is configured to generate a program voltage (Vpgm), a pass voltage (Vpass), a blocking voltage (Vblock) and a decoupling voltage (Vdcp) during a flash memory programming operation. The blocking voltage is generated at a level that inhibits inadvertent programming of an unselected memory cell(s). This voltage level of the blocking voltage is set so that Vdcp<Vblock≦Vpass<Vpgm. The decoupling voltage (Vdcp) has a magnitude that is greater than a maximum threshold voltage of an erased memory cell in the array and less than a minimum threshold voltage of a programmed memory cell in the array. A row selection circuit is also provided. This row selection circuit is electrically coupled to word lines in the array and to the voltage generator. The row selection circuit is configured to route the program, blocking, decoupling and pass voltages from the voltage generator to first, second, third and fourth word lines in the array, respectively, where the second word line is spaced between the first and third word lines.
