US Patent 7328415 Modeling blocks of an integrated circuit for timing verification

An integrated circuit may be divided into blocks and analyzed using a modeling algorithm which facilitates the concurrent analysis of a plurality of blocks forming an integrated circuit. In some cases, an electrical connectivity description of a block may be utilized to create static-timing representations that contain the logic that communicates with the boundary of a block. Once the models for the blocks forming an integrated circuit are generated, static-timing analysis may take place concurrently with all the relevant, identified paths.