Patent attributes
A test circuit for a flat panel display device is provided. The test circuit includes a substrate, a plurality of pixel structures, a plurality of signal lines and a plurality of shorting bar sets. The substrate includes at least one scan side, at least one data side and a pixel area. Each pixel structure formed in the pixel area having n sub-pixels, where n is a positive integer. The signal lines are formed on the substrate, and each signal line is connected to a corresponding sub-pixel. Each shorting bar set is formed on at least one of the at least one scan side and the at least one data side, wherein the shorting bar sets are electrically connected to the signal lines.