US Patent 7336111 Fast-locking digital phase locked loop

An apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.