US Patent 7336555 Refresh control circuit of pseudo SRAM

A refresh control circuit is provide for a pseudo SRAM that includes a plurality of banks. The refresh control circuit includes a buffer enable control unit that outputs a chip select internal control signal, and a bank selection unit that generates a single bank select signal or an all-bank select signal in response to the chip select internal control signal. The single bank select signal is enabled in an active operation to perform a refresh operation on one bank and the all-bank select signal is enabled in a standby operation to perform a refresh operation on all the banks.