Patent attributes
A demodulator with a phase-adjusting function including a detector including a delay detector delaying an input signal in delaying stages using a first clock obtained by frequency-dividing a sampling-clock at a first-ratio to output a delayed modulated signal, the sampling-clock having a predetermined frequency and a predetermined clock number, and a phase-adjustor which, when the stage number of the delaying stages obtained by dividing the predetermined clock number at the first-ratio does not become an integer, delays the input modulated signal using a second clock, the second clock obtained by frequency-dividing the sampling clock at a second-ratio, a ratio between the second-ratio and the first-ratio corresponding to a shortage in a final delaying stage to produce a phase-adjusted modulated signal that has been adjusted to cause the phase of the input modulated signal to coincide with the phase of the delayed modulated signal.
