Patent attributes
A low-power shift-and-negate unit within a fused multiply-adder circuit is disclosed. The shift-and-negate unit includes a large shift stage, a coarse shift stage, a negate stage and a fine shift stage. The large shift stage receives a first set of shift signals and a group of data signals to generate a group of first intermediate signals. The coarse shift stage receives a second set of shift signals and the group of first intermediate signals to generate a group of second intermediate signals and their complement signals. The large shift stage and the coarse shift stage are executed within a first single processor cycle. The negate stage receives a complement decision signal and the group of second intermediate signals along with their complement signals to generate a group of third intermediate signals. Finally, the fine shift stage receives a third set of shift signals and the group of third intermediate signals to generate a group of output signals. The negate stage and the fine shift stage are executed within a second single processor cycle.
