US Patent 7338898 MOS transistor and fabrication thereof
Patent 7338898 was granted and assigned to United Microelectronics Corporation on March, 2008 by the United States Patent and Trademark Office.
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Patent abstract
A method for fabricating a MOS transistor is described. A gate dielectric layer, a first barrier layer, an interlayer, a work-function-dominating layer, a second barrier layer and a poly-Si layer are sequentially formed on a substrate. The interlayer is capable of adjusting the work function of the work-function-dominating layer and wetting the surface of the first barrier layer. The above layers are then patterned into a gate, and a source/drain is formed in the substrate beside the gate.
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US Patent 07338898 MOS transistor and fabrication thereof US Patent 7338898 MOS transistor and fabrication thereof
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Patent Number
0733889800
Patent Number
733889800
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Official Website
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Infobox
Is a
Current Assignee
0
Patent Jurisdiction
Patent Number
073388980
Date of Patent
March 4, 2008
0Patent Application Number
111638940
Date Filed
November 3, 2005
0Official Website
Patent Primary Examiner
Edits on 27 Sep, 2022
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Infobox
Is a
Current Assignee
0
Patent Jurisdiction
Patent Number
073388980
Date of Patent
March 4, 2008
0Patent Application Number
111638940
Date Filed
November 3, 2005
0Official Website
Patent Primary Examiner
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US Patent 07338898 MOS transistor and fabrication thereof
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07338898
Date of patent
March 4, 2008
Patent application number
11163894
Date Filed
November 3, 2005
Patent primary examiner
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