Patent attributes
Various semiconductor structure embodiments include a substrate, a buried insulator over at least a portion of the substrate, a body region over the buried insulator, first and second source/drain regions to provide a channel region in the body region, a gate insulator over the channel region, and a gate over the gate insulator. The body region includes a silicon nitride region. Various system embodiments includes means for writing a memory cell into a first memory state by trapping charges in the charge trapping region to provide a silicon-on-insulator field effect transistor (SOI-FET) with a first threshold voltage, means for writing the memory cell into a second memory state by neutralizing charges in the charge trapping region to provide the SOI-FET with a second threshold voltage, and means for reading the memory cell using a channel conductance of the SOI-FET to determine a threshold voltage for the SOI-FET.
