Patent attributes
A memory card is provided with a transfer control circuit, a write control circuit and a judging circuit. The transfer control circuit outputs a transfer flag signal during the data transfer. The write control circuit outputs an internal busy signal during the data write operation. The judging circuit outputs a transfer interruption signal when a card selection signal of the host is negated during the input of the transfer flat signal and also outputs a suspension signal when the card selection signal is negated during the input of the internal busy signal. A CPU invalidates the data being transfer to interrupt the transfer process upon reception of the transfer interruption signal and completes, upon reception of the suspension signal, the process being executed and stays in the waiting condition. Consequently, even when the timing signal not conforming to the standards is transferred, the host can select the optimum processing operation from the internal processing conditions and thereby execute the selected operation.
