Patent attributes
A method and system is disclosed for creating a timing delay for power-on reset. A state machine is formed with three states. It resets a counter value to a predetermined number in an initial state, and increments the counter value for a predetermined number of reset cycles in a reset state until the counter value reaches a predetermined value for creating the time delay, and ends the reset state in a finish state if the counter reaches the predetermined value and if a randomly generated value matches a predetermined signature, wherein if in the reset state the randomly generated value does not match the signature or if in the finish state either the counter value does not reach the predetermined value or the randomly generated value does not match the signature, the initial state starts and subsequently enters the reset state after resetting the counter value.
