Patent attributes
An interrupt controller is provided for processing interrupt requests in a system having a plurality of data processing units operable to service those interrupt requests, each interrupt request having an associated priority level. The interrupt controller comprises request logic operable to receive an indication of unserviced interrupt requests, to apply predetermined criteria to determine which of said plurality of data processing units are candidate data processing units for servicing at least one of said unserviced interrupt requests, and to issue a request signal to each said candidate data processing unit. Priority encoding logic is operable to determine a highest priority unserviced interrupt request based on the associated priority levels of the unserviced interrupt requests. Further, handshake logic is operable to receive acknowledgement signals associated with said candidate data processing units replying to said request signals issued by the request logic, upon receipt of a first acknowledgement signal, the handshake logic being operable to allocate to the candidate data processing unit associated with that first acknowledgement signal the highest priority unserviced interrupt request as indicated by the priority encoding logic. By this approach, the highest priority unserviced interrupt request will be allocated to the data processing unit whose associated acknowledgement signal is first received by the handshake logic, and hence this increases the speed with which that highest priority interrupt request is serviced.
