US Patent 7352169 Testing components of I/O paths of an integrated circuit

Testing the components of I/O paths in an integrated circuit at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell tests the corresponding component (e.g., buffer) by launching data at a first time instance and receiving the result of the data at a second time instance, with the duration between the first time instance and the second time instance corresponding to the at-speed operation. If the data is received accurately, the component may be deemed to be operating accurately at-speed.