US Patent 7355895 Nonvolatile semiconductor memory and driving method the same

A nonvolatile semiconductor memory includes a memory cell array, a control circuit and an address control circuit. In the memory cell array, a plurality of memory cells are arranged in a matrix of rows and columns. The control circuit sets a write/erase mode in response to an erase instruction, and to count the erase instruction. The address control circuit generates a write address from an input address for a write operation based on a count value from the control circuit in the write/erase mode. A write order to the memory cells accessed based on a series of the write addresses in a current write operation is different from a write order to the memory cells accessed based on a series of write addresses in a previous write operation.