US Patent 7355909 Column redundancy reuse in memory devices

A method for column redundancy re-use includes arranging the memory array into a plurality of addressable first array columns and a plurality of addressable second array columns. The column redundancy structure is also arranged into an addressable first redundancy column and an addressable second redundancy column. A first column array which is found to be defective is replaced by mapping its address to the first redundancy column. In a similar manner, a second column array which is found to be defective is replaced by mapping its address to the second redundancy column.