Patent 7359463 was granted and assigned to Sony on April, 2008 by the United States Patent and Trademark Office.
The present invention establishes a metric calculation method. A constant calculation circuit 31 calculates constants V/2−A, V/2+A, and A/2, which are required to calculate branch metrics by using an average voltage V/2, corresponding to a parameter R input from an asymmetrical register, which is input from an average voltage register, and output them to adders 33, 35, and 36, respectively. A multiplier 32 multiplies an equalized signal yk by a value P of 1 or −1 input from a polarity register. A bit shifter 37 shifts by c bits A/2−yk, corresponding to the parameter R input from the asymmetrical register, which is input from the adder 36. That is, the bit shifter 37 multiplies A/2−yk by α, and outputs it to adders 38 and 39. However, when the parameter R is 0, the bit shifter 37 outputs 0 to the adders 38 and 39. The present invention can be applied to a recording and reproduction apparatus.